The present subject matter relates generally to manufacturing and, more particularly, to a method and apparatus for matching test equipment calibration.
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Generally, a set of processing steps is performed on a wafer using a variety of processing tools, including photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, implantation tools, etc. During the fabrication process various events may take place that affect the performance of the devices being fabricated. That is, variations in the fabrication process steps result in device performance variations. Factors, such as feature critical dimensions, doping levels, contact resistance, particle contamination, etc., all may potentially affect the end performance of the device.
After fabrication of the devices is complete, each wafer is subjected to preliminary functional tests. Wafers that pass these tests are then cut to singulate the individual die, which are then packed in substrates. Packed dies are then subjected to additional tests against the specification of customers' orders to determine performance characteristics such as maximum operating speed, power, caches, etc.
Exemplary tests include initial class tests (ICL) that is a preliminary test for power and speed. ICL testing is usually followed by burn-in (BI) and post burn-in (PBI) tests that test packaged die under specified temperature and/or voltage stress, and automatic test equipment (ATE) tests that test die functionality. Then, packaged dies with different characteristics go through system-level tests (SLT) in which they are tested against customer requirements on specific electrical characteristics. In SLT, packaged dies are tested in an actual motherboard by running system-level tests (e.g., variance test programs). After completion of the testing, the devices are fused, marked, and packed to fill customer orders. This back-end processing is commonly referred to as the test, mark, pack (TMP) process.
Based on the results of the performance tests each device is assigned a grade, which effectively determines its market value. In general, the higher a device is graded, the more valuable the device. However, some applications do not require high-end devices. Accordingly, maximizing the profitability of the fabrication facility does not necessarily equate to maximizing the output of high-grade devices.
During the testing process, many different ATE testers are employed to test devices in parallel. Various test programs are implemented to determine functionality and grade information. The particular test programs may vary by device or customer requirements. To provide consistent test results across the multiple ATE testers, various calibration procedures or preventative maintenance procedures are periodically performed. Even with such measures, it is possible that a tester may drift from its calibrated state or may operate inconsistently. As a result, devices tested with the degraded tester may not be graded or verified properly. In the case where the devices are graded lower than what is actually warranted, a direct loss in profit results.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.